A great example of science meets engineering to bridge the gap between theory and practice. This demo setup consolidates more than ten years of fundamental research in formal communication models and scheduling methods for next-generation distributed real-time systems, intersecting it with research on reconfigurable logic that makes possible to achieve the required computational performance and precision to validate them in practice.
The Atacama framework is the first fully functional, hardware-accelerated, and open-source, platform for Real-time Ethernet. The demonstration setup described here consists of a distributed buffer-less video processing application, which illustrates the capability to propagate scheduled real-time frames over multi-hop networks with unprecedented speed and timing accuracy, all without breaking compatibility with standard legacy components.
A short summary of technical feats:
Replicas of the complete setup are used at University of Waterloo and Universidad de Concepcion for demonstration and collection of data for research purposes. You can easily synthesize the devices and replicate every experiment using the code from the repository.
Additional credits:
The Atacama framework is the first fully functional, hardware-accelerated, and open-source, platform for Real-time Ethernet. The demonstration setup described here consists of a distributed buffer-less video processing application, which illustrates the capability to propagate scheduled real-time frames over multi-hop networks with unprecedented speed and timing accuracy, all without breaking compatibility with standard legacy components.
A short summary of technical feats:
- Full hardware-accelerated end-to-end path between distributed stations using augmented interfaces
- On-the-fly frame classification and processing on each augmented device
- 8 nanoseconds of jitter per physical connector in the path over 1 Gbit/s links (the uncertainty is inherent to physical medium)
- As deterministic as it gets
- Dynamic on-the-fly allocation of time slots for scheduled traffic for efficient bandwidth utilization
- More details about the project are available here.
- The latest work related to this project was recently accepted in the IEEE Transactions on Industrial Informatics.
- All source code ( HDL code, drivers, software, code for examples, etc.) is available here.
Replicas of the complete setup are used at University of Waterloo and Universidad de Concepcion for demonstration and collection of data for research purposes. You can easily synthesize the devices and replicate every experiment using the code from the repository.
Additional credits:
- Sebastian Fischmeister (theoretical foundations for real-time scheduling and supporting the overall deployment)
- Robert Trausmuth (original prototypes on which the final system is based on)
- Luis Araneda (video interfaces and processing applications, extensions and usability improvements)
For a detailed overview of the experiments shown below, see this:
| 1_-_case-studies.pdf |
|
Illustrating timing guarantees and robustness to injection of unscheduled best-effort traffic.
|
demo1-timing from G C on Vimeo. |
|
Complete setup, including dynamic allocation of time slots for scheduled real-time traffic.
|
demo2-full-dynamic from G C on Vimeo. |